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may 2014 docid023984 rev 2 1/42 AN4213 application note high-frequency ballast 2x58 w (t8 fluorescent tubes) based on a powerflat? 5x6 package by santina leo introduction fluorescent lamps are increasingly driven by electronic rather than electromagnetic ballasts mainly because fluorescent lamps can produce around 20% more light for the same input power when driven above 20 khz instead of 50/60 hz. operation at high frequency also eliminates both light flickering and audible noise. this application note describes the design calculations and test results of the steval- ilb010v1demonstration board able to drive 2x58 w linear t8 fluorescent tubes. the electronic ballast consists of two sections: a power factor correction pre-regulator (pfc), using the l6562a, and the lamp ballast stage with the l6569. the main purpose of this application note is to evaluate the electrical features of the new powerflat? 5x6 package and to compare its thermal results with that of the dpak package. the powerflat?5x6 package is used in the steval-ilb010v1 demonstration board shown below. figure 1. steval-ilb010v1 am17315v1 www.st.com
contents AN4213 2/42 docid023984 rev 2 contents 1 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pfc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 designing a tm pfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3.1 bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.2 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.3 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.4 boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.5 power mosfet selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.6 boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 l6562a biasing circuitry (pin by pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 dc/ac converter and lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 lamp requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.1 output inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.2 lamp preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 driving optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 power mosfet circuit optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 dc/ac converter waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 appendix a board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 appendix b bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
docid023984 rev 2 3/42 AN4213 contents appendix c layout layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of figures AN4213 4/42 docid023984 rev 2 list of figures figure 1. steval-ilb010v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. boost converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. inductor current waveform and power mosfet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. pfc electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. pin 1, 2: feedback network implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. multiplier setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. zcd resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. optimum power mosfet turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. boost pfc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. dc/ac converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. preheating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. lamp output voltage timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. lamp output voltage during preheating phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. lamp output voltage during ignition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. lamp output voltage during run-mode phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18. driving network optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 19. turn-off detail with r g =220 , speed off diode and c sn = 47 pf @ 230 v ac . . . . . . . . . . . . . . . 29 figure 20. turn-off detail with r g =220 , speed off diode and c sn =100 pf @ 230 v ac . . . . . . . . . . . . . . 29 figure 21. turn-on detail with r g = 220 , speed off diode and c sn = 47 pf @ 230 v ac. . . . . . . . . . . . . . 29 figure 22. turn-on detail with r g = 220 , speed off diode and c sn = 100 pf @ 230 v ac . . . . . . . . . . . . . 29 figure 23. turn-off detail with r g =47 , no speed off diode and c sn = 47 pf @ 230 v ac . . . . . . . . . . . . 30 figure 24. turn-off detail with r g = 47 , no speed off diode and c sn = 100 pf @ 230 v ac . . . . . . . . . . 30 figure 25. turn-on detail with r g = 47 , no speed off diode and c sn = 47 pf @ 230 v ac . . . . . . . . . . . 30 figure 26. turn-on detail with r g = 47 , no speed off diode and c sn = 100 pf @ 230 v ac . . . . . . . . . . 30 figure 27. stl13n60m2 during steady-state operation in half-bridge section @ 230 v ac . . . . . . . . . 32 figure 28. stl13n60m2 during turn-off in half-bridge section @230v ac (detail) . . . . . . . . . . . . . . . . 32 figure 29. stl13n60m2 during turn-on in half-bridge section @230v ac (detail) . . . . . . . . . . . . . . . . 33 figure 30. electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 31. bottom layout layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 32. top layout layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 33. silkscreen top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 34. silkscreen bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
docid023984 rev 2 5/42 AN4213 system description 1 system description figure 2. block diagram the electronic ballast consists of two sections: a power factor correction pre-regulator (pfc), using the l6562a, and the lamp ballast stage with the l6569. the power factor correction section is based on the l6562a. this is a current-mode pfc controller operating in transition mode (tm). it is especially designed for electronic lamp ballast applications (to better understand the l6562a characteristics, refer to an2761). the lamp ballast stage is based on the l6569 which is a high-voltage half-bridge driver with a built-in oscillator. the load consists of an l-c series resonant circuit with the lamps connected across the capacitors. this topology allows operating in zero-voltage switching, to reduce the transistor switching losses and the electromagnetic interference generated by the output wiring of the lamp. am17316v1 ac load cin co emi fi l te r pfc converter dc/ac 400vdc
pfc section AN4213 6/42 docid023984 rev 2 2 pfc section the power factor correction circuit reshapes the distorted input current waveform to approximate a sinusoidal current that is in phase with the input voltage. it is an index which measures the efficiency of the energy transfer from an ac source to a generic load. the input power factor (pf) is defined as the ratio of the real power (transferred to the output) over apparent power (see equation 1 ). equation 1 where: is a distortion factor and cos ? is the phase angle between input ac voltage and the fundamental current. two typical techniques used to achieve a sinusoidal input current waveform with low distortion are passive correction and active correction. passive pfc techniques shape the input current waveform by using a passive input filter consisting of inductors and capacitors. because it operates at the line frequency, 50 or 60 hz passive filters require relatively large fixed-value inductors and capacitors to reduce the low-frequency harmonic currents. it is difficult to achieve near unity power factor with passive filters. also, very large currents may circulate in the filter. however the passive filter is an effective pfc solution where the line frequency line voltage and load are relatively constant. an active pfc performs very well and is significantly smaller and lighter than the passive pfc circuit. the active pfc circuits operate at a higher switching frequency than the line frequency to allow a large reduction in the size and cost of passive filter elements. a typical active pfc circuit using switching techniques, located between the rectifier bridge and the filter capacitor, allows drawing a quasi-sinusoidal current from the mains, in phase with the line voltage. the boost circuit-based pfc topology is the most popular. the boost pfc circuit is a cheap solution to comply with the regulations. it can be implemented with a boost inductor, a controlled power switch, a catch diode, an output capacitor and, obviously, a control circuitry. (see figure 3 ). the boost inductor in the boost pfc circuit is in series with the ac power line. therefore the input current does not pulsate, minimizing conducted emi at the line. this allows the size of the emi filter and the conductors in the input circuit to be reduced. this topology accepts a wide input voltage range without an input voltage selector switch. the output voltage of a boost pfc circuit should be higher than the peak value of the maximum input voltage. cos * cos re 1 d rms rms rms rms rms rms k i i v i v i wer apparentpo alpower pf t = = = rms rms d i i k 1 =
docid023984 rev 2 7/42 AN4213 pfc section figure 3. boost converter circuit the boost converter can operate in two modes: discontinuous conduction mode (dcm) and continuous conduction mode (ccm). discontinuous conduction mode is when the power mosfet of the boost converter is turned on when the inductor current reaches zero after a dead time and turned off when the inductor current meets the input reference voltage. in this way, the input current waveform follows the input voltage one, therefore obtaining a power factor close to 1. dcm is suitable for power levels of 300 w or less. dcm uses larger cores and has higher i2r and skin-effect losses due to the larger inductor current swing. with the increased swing a larger input filter is also required. on the positive side, since in the discontinuous mode the power mosfet switches on when the inductor current is at zero, there is no reverse-recovery current (irr) specification required on the boost diode. this means that less expensive diodes can be used. continuous conduction mode (ccm) is when the current in the energy transfer inductor never reaches zero during the switching cycle. the power mosfet starts conducting when the current through itself is not zero. continuous conduction mode (ccm) is suitable for high power ratings (>300 w). the voltage swing is less than in dcm resulting in lower i2r losses and the lower ripple current results in lower inductor core losses. less voltage swing also reduces emi and allows for a smaller input filter to be used. unfortunately, since the power mosfet is not being turned on when the current of the inductor is at zero, a very fast reverse-recovery diode is required to keep losses to a minimum. transition conduction mode which is typically used in lighting applications represents a good cost-benefit compromise. in the transition mode approach, the switch-on time is held constant during the line cycle and the switch is turned on when the inductor current falls to zero, so that the converter operates at the boundary between continuous and discontinuous conduction mode. in this way, the freewheeling diode is turned off softly (no recovery losses) and the switch is turned on at zero current, so the commutation losses are reduced. besides the simplicity and the few external parts required, this system minimizes the inductor size due to the low inductance value needed. on the other hand, the high current ripple on the inductor involves high rms current and high noise on the rectified main bus, which needs a heavier emi filter to be rejected. these drawbacks limit the use of the tm pfc in a lower power range (typically below 200 w). am17317v1 ac controller load il l cin q iq id ic co io
pfc section AN4213 8/42 docid023984 rev 2 the principle scheme is shown in figure 4 . the instantaneous input current is constituted by a sequence of triangles whose peaks are proportional to the line voltage. thus, the average input current becomes proportional to the line voltage without duty-cycle modulation during the line cycle. in this application note boost topology working in transition mode is considered. figure 4. inductor current waveform and power mosfet timing am17318v1 i sw i d i l i ac i lpk mosfet off on
docid023984 rev 2 9/42 AN4213 designing a tm pfc 3 designing a tm pfc 3.1 input specification the first consideration for designing a new boost pfc converter is a detailed specification of the operating conditions of the circuit that is needed for the calculation. in this example a 116 w, single-input range mains pfc circuit has been considered. the l6562a integrates an ovp in order to prevent excessive output voltage that can overstress the output components and the load. ? maximum output overvoltage: the pfc minimum switching frequency is one of the main parameters used to dimension the boost inductor. the switching frequency at low mains on the top of the sinusoid and at full load conditions has been considered. it must be higher than the audio bandwidth in order to avoid audible noise and it must not interfere with the l6562a minimum internal starter period. on the other hand, if the minimum frequency is set too high, the circuit shows excessive losses at a higher input voltage. the typical minimum frequency range is 20 - 50 khz. ? minimum switching frequency (khz): in order to properly select the power components of the pfc, the maximum operating ambient temperature around the pfc circuitry must be known. the designer must take into consideration that it is the temperature at which the pfc components are working and not the maximum external operating temperature of the entire equipment. ? maximum ambient temperature (c): table 1. specified parameters converter specification data and fixed parameters symbol description values v ac(min) mains voltage range 185 v ac v ac(max) 265 v ac fl minimum mains frequency 47 hz p out rated output power 116 w v out regulated dc output voltage 400 v =p out /p in expected efficiency 90% pf expected power factor 0.99 v v ovp 40 = khz f sw 35 min = c t ambx = 50
designing a tm pfc AN4213 10/42 docid023984 rev 2 3.2 operating conditions the first step is to define the main parameters of the circuit as follows: ? rated dc output current: equation 2 ? maximum input power: equation 3 ? rms input current: equation 4 ? peak inductor current: equation 5 ? rms inductor current: equation 6 ? ac inductor current: equation 7 the current flowing into the inductor can be divided in two parts depending on the instant of conduction. during the on time, it increases from zero up to its peak value and flows in the switch, otherwise during the off time the current decreases from its peak down to zero and it flows into the diode. therefore, in order to calculate the losses of these two elements, it is useful to know the rms current which flows into the switch and into the diode. ? rms switch current: equation 8 a v p i out out out 29 . 0 400 116 = = = w p p out in 129 9 . 0 116 = = = a pf v p i ac in in 7 . 0 99 . 0 185 129 min = ? = ? = a i i in lpk 97 . 1 2 2 = ? = a i i in lrms 8 . 0 3 2 = ? = a i i i in lrms lac 38 . 0 2 2 = ? = = swrms i a v v i out ac lpk 51 . 0 * 9 2 4 6 1 min = ?
docid023984 rev 2 11/42 AN4213 designing a tm pfc ? rms diode current: equation 9 3.3 power section design 3.3.1 bridge rectifier the input rectifier bridge can use standard, slow-recovery, low-cost devices. typically a 600 v device is selected in order to have a good margin against mains surges. equation 10 equation 11 the power dissipated on the bridge is calculated using equation 12 : equation 12 where r diode and v th are given in the technical datasheet. 3.3.2 input capacitor the input capacitor has to attenuate the switching noise due to the high-frequency inductor current ripple. the worst condition happens on the peak of the minimum rated input voltage (v inmin =185 v). the maximum high-frequency voltage ripple across c in is usually imposed between 5% and 20% of the minimum rated input voltage. this is expressed by a coefficient r (from 0.05 to 0.2) as an input design parameter. ? ripple voltage coefficient (%): r = 0.2 taking into account a minimum half-bridge switching frequency of 35 khz and an output power of 116 w, the input capacitor can be determined by the following equation. equation 13 a v v i i out ac lpk drms 59 . 0 * 9 2 4 min = = a i i in inrms 49 . 0 2 * 2 = = a i i in avg in 31 . 0 * 2 = = ? avg in th inrms diode brid ge i v i r p ? + = * * 4 * * 4 2 min min * * * 2 ac sw in in v r f i c = f c in 086 . 0 185 * 2 . 0 * 35 * 14 . 3 * 2 7 . 0 = =
designing a tm pfc AN4213 12/42 docid023984 rev 2 c in has been selected equal to 150 nf. of course a bigger capacitor provides a benefit in terms of emi, but on the other hand worsens the thd, mainly at high mains voltage. for this reason the right trade-off is needed in order to have the best performance. a good quality film capacitor must be selected in order to provide good filtering effectiveness. 3.3.3 output capacitor the selection of the output bulk capacitor c out depends on the dc output voltage, the allowable overvoltage and the converter output power. with these values, the output capacitor can be calculated using the following equation: equation 14 to obtain the smallest possible ripple and good reliability, a commercial capacitor of 56 f, 450 v has been selected. 3.3.4 boost inductor in the transition mode control, the inductor value needs to be calculated to start the next switching cycle at zero current. the boost inductor determines the operating frequency of the converter. first, the inductance value must be defined. the inductance (l) is usually determined so that the minimum switching frequency is greater than the maximum frequency of the l6562a internal starter, in order to ensure correct tm operation. assuming unity pf, it is possible to write: equation 15 equation 16 t on and t off are, respectively, the on-time and the off-time of the power mosfet, i lpk is the maximum peak inductor current in a line cycle and is the instantaneous line phase in the interval (0, ). the instantaneous switching frequency in a line cycle is given by equation 17 : equation 17 f v v f p c out out main out out 49 10 * 400 * 47 * 4 116 * * 4 = () ac lpk ac lpk ac on v i l v i l v t * 2 * sin * * 2 sin * * , = = ? ? ? () ? ? ? sin * * 2 sin * * , ac out lpk ac off v v i l v t ? = () () out ac out ac in off on ac sw v v v v p l t t v f ? ? sin * * 2 * * * 2 1 1 , 2 ? = + =
docid023984 rev 2 13/42 AN4213 designing a tm pfc the switching frequency is minimum at the top of the sinusoid and it is maximum at the zero-crossing of the line voltage ( ? =0, = sin ? =0) where t off = 0 s. the absolute minimum frequency f swmin can occur at either the maximum v acmax or the minimum mains voltage v acmin , so the inductor value is calculated by the formula: equation 18 where v ac can be either v acmin or v acmax , whichever gives the lower value for l. the values of the inductor at low mains and at high mains, respectively l(v acmax ) and l(v acmin ) are given by following equations: equation 19 equation 20 at this point the minimum value has to be taken into account. it becomes the maximum inductance value for pfc dimensioning. for this application a 0.5 mh boost inductance has been selected. 3.3.5 power mosfet selection the main switch selection is driven by the amount of allowable power dissipation. it is important to choose a device that minimizes gate charge and capacitance and minimizes the sum of switching and conduction losses at a given frequency. the breakdown voltage is fixed just by the output voltage, plus the allowable overvoltage and a safety margin. the conduction losses are given by: equation 21 ? ? ? ? ? ? = ? = 1 sin 2 ? ? () () 2 * 2 * 2 ac out ac ac v v v v l ? = () () () () mh v l v p f v v v v l ac out in sw ac out ac ac 36 . 1 400 * 129 * 10 * 35 * 2 185 * 2 400 * 185 * * * 2 * 2 * 3 2 max min min 2 mi n max = ? = ? ? = () () () () mh v l v p f v v v v l ac out in sw ac out ac ac 51 . 0 400 * 129 * 10 * 35 * 2 265 * 2 400 * 265 * * * 2 * 2 * 3 2 ma x min max 2 max mi n = ? = ? ? = () () 2 * ac swrms dson cond v i r p =
designing a tm pfc AN4213 14/42 docid023984 rev 2 where, as given in equation 8 : the switching losses in the power mosfet occur only at turn-off because of tm operation and can be expressed by: equation 22 this equation represents the crossing between the power mosfet current that decreases linearly during the fall time and the voltage on the power mosfet drain that increases. in fact during the fall time the current of the boost inductor flows into the parasitic capacitance of the power mosfet, charging it. for this reason switching losses depend on the total drain capacitance. at turn-on the losses are due to the discharge of the total drain capacitance inside the power mosfet itself. the capacitive losses are given by: equation 23 where c d is the total drain capacitance and v mos is the drain voltage at power mosfet turn-on. based on the above considerations, the power mosfet device selected is the stl13n60m2. this device is an n-channel power mosfet developed using a new generation of mdmesh ii plus tm low q g . this revolutionary power mosfet associates a vertical structure to the company's strip layout to yield one of the world's lowest on- resistance and gate charge. this choice is confirmed by the good electrical performance and thermal behavior. 3.3.6 boost diode selection a fast-recovery boost diode is used. the value of its dc and rms current (see equation 9 ), useful for the calculation of the losses, are both: equation 24 the conduction losses can be estimated as follows: equation 25 where, v th (threshold voltage) and r d (differential resistance) are parameters of the diode. out ac lpk swrms v v i i min * 9 2 4 6 1 ? = () () lrms sw g lrms out gd ac switch i f i i v q v p 2 * * = () () ac sw mos d ac cap v f v c v p * * 2 1 2 = a i i out d 29 . 0 = = 2 * * drms d d th don i r i v p + =
docid023984 rev 2 15/42 AN4213 designing a tm pfc the breakdown voltage is fixed by the same criterion as the power mosfet. a minimum breakdown voltage of 1.2*(v out - v ovp ) and a current rating higher than 3*i out , can be chosen for a rough initial selection of the rectifier. in this 116 w application an stth1l06 (600 v, 1 a) has been selected. from the stth1l06 datasheet, v th is 0.89v and r d is 0.165 , therefore substituting these values in equation 25 , we have: 3.4 l6562a biasing circuitry (pin by pin) this section explains the dimensioning of the biasing circuitry pin-by-pin. for reference, the relevant components have been highlighted in the figure below. figure 5. pfc electrical schematic () w a a v p don 315 . 0 59 . 0 * 165 . 0 29 . 0 * 89 . 0 2 = + = am17319v1 ac in v 1 comp 2 3 mu lt 4 cs zcd gnd gd vcc 5 6 7 8 + 400vdc rmulth rmultl rzcd rsense ntc routh routl ccomp l r m u l t l c c vin(vac)
designing a tm pfc AN4213 16/42 docid023984 rev 2 pin 1, 2: feedback network implementation figure 6. pin 1, 2: feedback network implementation pin 1 (inv) : inverting input of the error amplifier. the information on the output voltage of the pfc pre-regulator is fed into this pin through a resistor divider (r outh and r outl ). the internal reference on the non-inverting input is 2.5 v (typ), while the dis intervention threshold is 27 a. r outh and r outl are then selected as follows: equation 26 equation 27 the commercial selected values are two resistors in series each 680 k for r outh and r outl equal to 8.2 k . pin 2 (comp) : output of the error amplifier. a compensation network is placed between this pin and inv (pin 1) in order to achieve stability of the voltage control loop and ensure high power factor and low thd. it has to be designed with a narrow bandwidth in order to avoid that the system rejects the output voltage ripple that would bring high distortion of the input current waveform. setting a bandwidth (bw) from 20 to 30 hz, c comp (as shown in figure 6 ) can be calculated as follows: equation 28 am17320v1 inv 1 comp 2 3 mu lt 4 cs zcd gnd gd vcc 5 6 7 8 l6562a hv routh routl = = k a v r ovp outh 1480 27 = = ? = ? = k r r v v r r outh outl out outl outh 3 . 9 159 159 1 5 . 2 () f bw iir r c outl outh comp 1 2 1 ? ? =
docid023984 rev 2 17/42 AN4213 designing a tm pfc pin 4 (cs) : input to the pwm comparator figure 7. sense resistor the current flowing in the power mosfet is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine power mosfet turn-off. the power mosfet stays in the off-state until the pwm latch is reset by the zcd signal. the sense resistor value can be calculated as follows: equation 29 where: ? i lpk is the maximum peak current in the inductor, equal to 1.99 a ? v csmin = 1 v is the minimum voltage allowed on the l6562a current sense (given in the datasheet). for this project the selected commercial value for r s is 0.47 . using this value and considering the maximum voltage v csmax = 1.16 v allowed on the l6562a (as given in the datasheet), the maximum peak of the inductor current can be calculated as follows: equation 30 the calculated i lpkx is the saturation inductor current and it is used for calculating the winding number of the inductor and its air gap. am17321v1 in v 1 comp 2 3 mu lt 4 cs zcd gnd gd vcc 5 6 7 8 l6562a hv rsense 502 . 0 min lpk cs s i v r a r v i s cs lpkx 5 . 2 max = =
designing a tm pfc AN4213 18/42 docid023984 rev 2 pin 3 (mult) : main input to the multiplier. figure 8. multiplier setting this pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. the multiplier can be described by the relationship: equation 31 where: ? v cs (multiplier output) is the reference for the current sense ? k = 0.38 (typ) is the multiplier gain ? v comp is the voltage on pin 2 ? v mult is the voltage on pin 3 first, the maximum peak value for v mult max is selected. this value has to be selected in the range from 0 up to 3 v. typically, it should be less than 3 v in case of single mains equation 32 where 1.1 v is the multiplier maximum slope which is given in the datasheet. am17322v1 vin(vac) rmulth rmultl in v 1 comp 2 3 mult 4 cs zcd gnd gd vcc 5 6 7 8 l6562a () mult comp cs v v v k v ? ? = 5 . 2 v v v r i v ac ac s lpk multpk 21 . 1 185 265 1 . 1 47 . 0 99 . 1 1 . 1 min max max = ? ? = ? ? =
docid023984 rev 2 19/42 AN4213 designing a tm pfc in this way, the resistor divider will be such that equation 33 supposing a 200 a current flowing into the multiplier divider, r multl is calculated as follows: equation 34 taking into account this value and from equation 33 : equation 35 the selected values are r multl = 8.2 k and r multh = 2 m pin 5 (zcd): zero-current detection figure 9. zcd resistor the zero-current detection (zcd) block switches the external power mosfet on as the voltage across the boost inductor reverses, just after the current through the boost inductor has gone to zero. this feature allows transition mode operation. the zcd pin is connected to the auxiliary winding of the inductor boost through a limiting resistor. 3 max max 10 24 . 3 265 41 . 1 21 . 1 2 ? ? = ? = = + = ac mu lt multh mu ltl multl p v v r r r k = ? = = ? k a v r mult multl 2 . 6 10 200 21 . 1 200 6 = ? = m r k k r multl p p multh 9 . 1 1 am17323v1 vin(vac) rmulth rmultl in v 1 comp 2 3 mult 4 cs zcd gnd gd vcc 5 6 7 8 l6562a
designing a tm pfc AN4213 20/42 docid023984 rev 2 the maximum main-auxiliary winding turn ratio, nmax, has to ensure that the voltage delivered to the pin during the off-time of the power mosfet is sufficient to arm the zcd circuit. equation 36 the minimum value of the limiting resistor can be found assuming 0.8 ma current through the pin and considering the maximum voltage across the auxiliary winding with a selected turn ratio n = 10. the actual value can be fine-tuned in order to make the turn-on of the power mosfet occur exactly on the valley of the drain voltage oscillation (the boost inductor, completely discharged, is ringing with the drain capacitance, as shown in the figure below). this will minimize the power dissipation at turn-on. figure 10. optimum power mosfet turn-on equation 37 equation 38 7 . 15 15 . 1 4 . 1 2 max sec ? ? ? n v v n n n ac out ondary primary am17324v1 vout vdrain vipk vzcd 5.7 0.7 1.4 t t = ? = ? = k ma ma v n v r zcdh out 9 . 42 8 . 0 7 . 5 10 400 8 . 0 1 = ? ? = ? = k ma ma v n v r zcdl ac 8 . 46 8 . 0 0 10 265 2 8 . 0 2 max 2
docid023984 rev 2 21/42 AN4213 designing a tm pfc where v zcdh = 5.7 v (typ) and v zcdl = 0 (typ) are given in the datasheet. we consider the highest value, for this reason the selected limiting resistor is r zcd = 47 k . the complete boost pfc schematic is given in the following figure. figure 11. boost pfc section am17325v1 ac in v 1 comp 2 3 mu lt 4 cs zcd gnd gd vcc 5 6 7 8 + 400vdc fuse c1 l1 c20 d1 d2 d3 d4 c3 r25 r26 r2 r17 r18 l2 r20 r5 r4 r9 d5 ntc c7 r16 r7 r22 c6 c19 r27 c23 + d12 c24 c25
dc/ac converter and lamp AN4213 22/42 docid023984 rev 2 4 dc/ac converter and lamp the dc/ac converter uses a half-bridge voltage-fed topology with two power mosfets driven by the l6569 driver. it is a high-voltage half-bridge driver with an oscillator inside. here below is the complete electrical schematic of dc/ac inverter in half-bridge topology: figure 12. dc/ac converter voltage-fed series resonant half-bridge inverters are currently used for fluorescent lamps. this topology makes easy to operate in zero-voltage switching (zvs) resonant mode, dramatically reducing transistor switching losses and the electromagnetic interference. this type of inverter can operate up to 150 khz in zvs mode. for this project, the frequency has been selected between 50 and 100 khz, specifically ? run 57 khz. the frequency of the internal oscillator can be programmed using an external circuitry composed of a resistor r f and a capacitor c f . the nominal oscillator frequency can be calculated using the following equation 39 : equation 39 from the above equation, imposing c f =560 pf, r f will be equal to 22 k . 4.1 bootstrap circuit the bootstrap block is needed to supply the high-voltage section. this function is normally accomplished by a high-voltage fast-recovery diode. the l6569 has an internal bootstrap circuit that replaces the external diode. the bootstrap capacitor (c boot ) is charged every time the low-side driver is on and the output pin is below the supply voltage (v dd ) of the gate driver. the bootstrap capacitor is discharged only when the high-side switch is turned on. this bootstrap capacitor is the supply voltage (v bs ) for the high circuit section. am17326v1 vs 1 rf 2 3 cf 4 gnd boot hvg out lvg 8 7 6 5 l6569 rf + cf lamp lamp dc 400vdc cboot csn ptc ptc l3 l4 + khz c r c r f f f f f osc 57 3863 . 1 1 2 ln 2 1 = ? ? = ? ? =
docid023984 rev 2 23/42 AN4213 dc/ac converter and lamp the first parameter to take into account is the maximum voltage drop that we have to guarantee when the high-side switch is in the on state. the maximum allowable voltage drop (v boot ) depends on the minimum gate drive voltage (for the high-side switch) to maintain. if v gsmin is the minimum gate-source voltage, the capacitor drop must be: equation 40 where: ? v dd is supply voltage of the gate driver [v]; ? v f is the bootstrap diode forward-voltage drop [v]. the value of the bootstrap capacitor is calculated by: equation 41 where, q total is the total amount of the charge supplied by the capacitor. the total charge supplied by the bootstrap capacitor is calculated using equation 42 : equation 42 where: ? q gate is the total gate charge ? i lkcap is the bootstrap capacitor leakage current ? i lkgs is the switch gate-source leakage current ? i qbs is the bootstrap circuit quiescent current ? i lk is the bootstrap circuit leakage current ? i lkdiode is the bootstrap diode leakage current ? t on is the high-side switch-on time ? q ls is the charge required by the internal level shifter, which is set to 3 nc for all hv gate drivers. the capacitor leakage current is important only if an electrolytic capacitor is used, otherwise this can be neglected. recommended values for the bootstrap capacitor are within the range of 100 nf~570 nf, but the right value must be selected according to the application in which the device is used. when the capacitor value is too large, the bootstrap charging time slows and the low-side on-time might be not long enough to reach the bootstrap voltage. for this project the selected value is 100 nf/400 v. the output drivers drive an external n- channel power mosfet. the internal logic ensures a deadtime (typ 1.25 s) to avoid cross- conduction of the power devices. the selected power device is stl13n60m2. gsmin f dd boot v v v v ? ? = boot total boot v q c = () ls on lkdiode lk qbs lkgs lkcap gate total q t i i i i i q q + ? + + + + + =
dc/ac converter and lamp AN4213 24/42 docid023984 rev 2 4.2 lamp requirements 4.2.1 output inductor design the output inductor should be designed to allow a sufficient peak ignition current without saturating. this is important as the ballast will be unable to ignite if it cannot deliver sufficient voltage to the lamp. the ignition current depends on the type of the lamp being used and must be kept to a minimum by ensuring that the cathodes are sufficiently preheated. to minimize eddy current losses in the inductor, multi-stranded wire for the windings should be used. it is important to have a large enough air gap to produce the highest available peak current before allowing the inductor to saturate. when the cores are hot, the saturation point and hence the peak current for the inductor will be lower, therefore a poorly designed inductor may result in the ballast failing to ignite the lamp during an attempted hot re-strike. the value of the output inductor is given by following equation: equation 43 4.2.2 lamp preheating it is essential that the lamp be sufficiently preheated before ignited. in order to achieve the maximum possible lamp life, it is necessary to heat the cathodes to the correct temperature before ignition. accelerated deterioration occurs if lamps are ignited when the cathodes are either not sufficiently heated or overheated. the preheating of the cathodes allows an easy strike of the lamp, reducing ignition voltage. during preheating time the lamp is characterized by high impedance and the current flows through the filament. its resistance value is strictly dependent on the lamp model. typically these filaments show an initially low value (a few ohms) that will increase by 5 times during the preheating. one method to obtain the preheating cathodes is to adopt a ptc resistor. figure 13 shows its typical connection. figure 13. preheating circuit run run in p f v l 2 2 2 = am17327v1 ptc lres cres c?res c??res
docid023984 rev 2 25/42 AN4213 dc/ac converter and lamp at startup when the ptc is cold, it can be considered as a short-circuit, the circuit operating frequency is determined by c?res and lres (we can neglect cres). during the preheating the current flows through the ptc and c?res heats both the cathodes and the ptc at the same time. the value of c?res must be chosen in order to avoid high voltage on the lamp and consequent switch-on. when the ptc is hot (end of preheating) its resistance increases until it can be considered as an open circuit. in this case the current flows through the series formed by c??res and c?res. therefore the equivalent capacitance across the lamp becomes lower than the initial value, increasing the capacitive reactance and allowing the tube ignition. we can summarize the turn-on sequence in three phases: preheating, ignition and normal lamp operation. the preheating of the lamp filaments is achieved by a high switching frequency f pre , to ensure that a current flows in the filaments without lamp ignition. in fact the initial voltage applied across the lamp is below the strike potential. the duration of the preheating period t pre is set by the capacitor c?res together with lres. the choice of this time is strictly dependent on the lamp type. the ignition sequence begins after t pre . during the ignition phase, the frequency shifts from f max to f min (that is the normal operation frequency) in a period tsh. the voltage across the lamp increases causing the ignition. at the end of the ignition time the frequency reaches the normal operation value, f min , and the lamp is in run mode (as shown in figure 14 ). figure 14. lamp output voltage timing diagram the following figures indicate the preheating, ignition and run mode phases, respectively. am17328v1 time vlamp vph vign ignition ramp vrun preheat fmax frequency ignition phase run ignition fmin tpre tsh trun fmin normal operation
dc/ac converter and lamp AN4213 26/42 docid023984 rev 2 figure 15. lamp output voltage during preheating phase figure 16. lamp output voltage during ignition phase am17329v1 vlamp ilamp vlamp preheating phase vlamp ilamp vlamp preheating phase am17330v1 vlamp ilamp vlamp ilamp ignition phase vlamp ilamp vlamp ilamp ignition phase
docid023984 rev 2 27/42 AN4213 dc/ac converter and lamp figure 17. lamp output voltage during run-mode phase am17331v1 vlamp ilamp vlamp ilamp run mode phase vlamp ilamp vlamp ilamp run mode phase
driving optimization AN4213 28/42 docid023984 rev 2 5 driving optimization a driving network optimization has been performed with the main purpose to have thermal and dynamic behavior of the devices compliant to the features of the system. 5.1 power mosfet circuit optimization here below is the electrical schematic concerning the driving circuit of the power mosfet. figure 18. driving network optimization an rc snubber network, r = 180 and c sn =47 pf, has been inserted in order to avoid a voltage spike and voltage oscillation across the power mosfet during its turn-off. furthermore, limiting the rise slope of the power mosfet voltage, v ds / t, the cross between voltage and current is also reduced resulting in less switching losses during turn- off. on the other hand, a too high value involves a peak on the current during turn-on. so a right trade-off has to be found in order to balance the switching losses during turn-off and turn-on and to have the best performance of the device. am17332v1 hv r csn rg d rsense
docid023984 rev 2 29/42 AN4213 driving optimization the driving circuit, r g = 220 and the diode d, allows the power mosfet to not have turn- on too quickly, reducing the discharge of snubber capacitor and consequently guaranteeing negligible switch-on losses and thanks to the diode, it allows the fastest discharge of parasitic capacitance of the power mosfet and therefore speeds up the switch-off. a comparison has been performed between two different driving networks in order to find the best solution. the following figures show the waveforms of various conditions. figure 19. turn-off detail with r g =220 , speed off diode and c sn = 47 pf @ 230 v ac figure 20. turn-off detail with r g =220 , speed off diode and c sn =100 pf @ 230 v ac figure 21. turn-on detail with r g = 220 , speed off diode and c sn = 47 pf @ 230 v ac figure 22. turn-on detail with r g = 220 , speed off diode and c sn = 100 pf @ 230 v ac am17333v1 s s d d v v d d i i s s g g v v e eo of ff f am17334v1 s s d d v v d d i i s s g g v v f f f f o o e e am17335v1 s s d d v v d d i i s s g g v v n n o o e e am17336v1 s s d d v v d d i i s s g g v v n n o o e e
driving optimization AN4213 30/42 docid023984 rev 2 figure 23. turn-off detail with r g =47 , no speed off diode and c sn = 47 pf @ 230 v ac figure 24. turn-off detail with r g = 47 , no speed off diode and c sn = 100 pf @ 230 v ac figure 25. turn-on detail with r g = 47 , no speed off diode and c sn = 47 pf @ 230 v ac figure 26. turn-on detail with r g = 47 , no speed off diode and c sn = 100 pf @ 230 v ac am17337v1 s s d d v v d d i i s s g g v v f f f f o o e e am17338v1 s s d d v v d d i i s s g g v v f f f f o o e e am17339v1 s s d d v v d d i i s s g g v v n n o o e e am17340v1 s s d d v v d d i i s s g g v v n n o o e e
docid023984 rev 2 31/42 AN4213 driving optimization here below is the summary table, in terms of dissipated energy during both turn-on and turn-off detail. as table 2 shows, the best compromise in terms of switching losses, is to have a smaller snubber capacitor, c sn = 47 pf, in order to reduce the peak on the drain current during turn- on (as shown in figure 21 ) and r g = 220 with speed off diode in order to speed up the device turn-off (as shown in figure 19 .). in fact a greater r g provides a slower switch-on of the power mosfet, reduces the snubber capacitor discharge, guaranteeing negligible power losses during turn-on. table 2. summary table of dissipation energy driving conditions e on (j) e off (j) e tot (j) r g =220 , speed off diode, c sn = 47 pf 1.27 6.39 7.66 r g =220 , speed off diode, c sn = 100 pf 2.05 6.22 8.72 r g =220 , no speed off diode, c sn = 47 pf 1.25 12.46 13.71 r g =220 , no speed off diode, c sn = 100 pf 1.66 10.56 12.22
dc/ac converter waveforms AN4213 32/42 docid023984 rev 2 6 dc/ac converter waveforms the figures below depict the waveforms during steady-state operation and turn-off and turn- on detail related to the dc/ac converter stage which adopts a half-bridge voltage-fed topology. the device is stl13n60m2 which works at ~57 khz. figure 27. stl13n60m2 during steady-state operation in half-bridge section @ 230 v ac figure 28. stl13n60m2 during turn-off in half-bridge section @230v ac (detail) am17341v1 vds id vgs am17342v1 vds id vgs
docid023984 rev 2 33/42 AN4213 dc/ac converter waveforms figure 29. stl13n60m2 during turn-on in half-bridge section @230v ac (detail) it?s clear that the device has good performance in the half-bridge section. in fact, the cross during turn-off (see figure 28 ) is very low, resulting in low power dissipation. am17343v1 vds id vgs
experimental results AN4213 34/42 docid023984 rev 2 7 experimental results the experimental results have been measured with different input voltages and leaving the board exposed to room temperature (25 c). the devices have been kept soldered on the pcb. temperature has been detected using an infrared thermal camera pointed on the package of the devices. the test equipment used is provided below as well as the test conditions: ? input voltage: 185 v ac - 230 v ac - 265 v ac ? test equipment: ? agilent ac power source/analyzer 6813b ? flir system thermal camera ? lecroy 64xi-a oscilloscope ? lecroy active current probe cp030 ? lecroy active differential voltage probe adp305 ? ambient temperature: 25c. the table below shows electrical and thermal results obtained with both packages, dpak and powerflat? 5x6, at different input voltages. changing input voltage, the main electrical parameters of the pfc and thd suggest that the application performances are very good. the temperatures of the two packages are not so different and the devices work within safety conditions. table 3. main electrical and thermal results @ 25 c ambient temperature device v in (v) l in (a) power factor thd (%) pin (w) t hb (c) t pfc (c) std13n60m2 (dpak) 185 0.576 0.997 7.5 106 70 64.2 stl13n60m2 (powerflat? 5x6) 0.569 0.997 7.2 104.9 71.9 67 std13n60m2 (dpak) 230 0.465 0.995 8.1 106.4 71 66.5 stl13n60m2 (powerflat? 5x6) 0.456 0.994 8 104.4 72 69 std13n60m2 (dpak) 265 0.404 0.991 9 106.3 71.8 70.4 stl13n60m2 (powerflat? 5x6) 0.395 0.99 8.5 103.9 72.2 73
docid023984 rev 2 35/42 AN4213 conclusion 8 conclusion the proposed design of the electronic ballast has shown the capability of the demonstration board to drive 2x58 w fluorescent lamps with very good electrical and thermal performance. the choice of components and the optimization of the power devices guarantee the highest pf and lowest thd. the main purpose of this exercise was to evaluate the electrical and thermal features of the powerflat? 5x6 compared to the dpak package. the powerflat? 5x6 package showed comparable thermal results. for both package options the temperature is fully compliant with the absolute maximum rating limit in the datasheet specification.
board description AN4213 36/42 docid023984 rev 2 appendix a board description figure 30. electrical schematic am17344v1 ac in v 1 comp 2 3 mu lt 4 cs zcd gnd gd vcc 5 6 7 8 + fuse c1 l1 c20 d1 d2 d3 d4 c3 r25 r26 r2 r17 r18 l2 r20 r5 r4 r9 d13 ntc c7 r16 r7 r22 c6 c19 r27 c23 + d12 c24 c25 vs 1 rf 2 3 cf 4 gnd boot hvg out lvg 8 7 6 5 l6569 r10 + c8 lamp lamp c19 c21 ptc ptc l3 l4 r24 l6562a c22 c13 d6 d7 r11 c11 u4 u3 q1 q3 q4 r19 r13 c11 c12 c14 c15 r14 r15 c16
docid023984 rev 2 37/42 AN4213 bill of material appendix b bill of material table 4. board bill of material reference qty value/part number description r2/r22 2 8.2 k /0.25 w rc07 r4 1 56 k smd 1206 r20 1 47 k /0.25 w rc07 r5 1 220 k smd 1206 r7/r16 2 680 k /0.25 w rc07 r9 1 0.47 k /0.5 w rc07 r10 1 22 k /0.25 w rc07 r11/r28 2 100 k /2 w rc07 r13/r19 2 47 k smd 1206 r17/r18 2 270 k /0.25 w rc07 r24 1 10 k /0.25 w rc07 r25/r26 2 1 m /0.5 w rc07 r27 1 180 k /0.25 w rc07 c1/c20 2 220 nf/305 v ac x2 metallized polypropylene capacitor c3 1 150 nf/630 v dc plastic capacitor c6 1 10 nf/100 v dc metallized polyester capacitor c7 1 56 f/450 v electrolytic capacitor c8 1 560 pf/50 v ceramic capacitor c9 1 100 nf/400 v dc polyester capacitor c16 1 100 nf/630 v dc polyester capacitor c10 1 560 pf/500 v dc ceramic capacitor c11/c14 2 15 nf/630 v dc metallized polypropylene capacitor c12/c15 2 22 nf/630 v dc phe450 film capacitor c13 1 22 f/50 v electrolytic capacitor c19 1 1 f/100 v polyester capacitor c21 1 2.2 nf/1000 v ceramic capacitor c22 1 100 nf/100 v dc polyester capacitor c23 1 47 nf/500 v dc ceramic capacitor c24 1 220 nf/100 v metallized polyester capacitor c25 1 10 f/>25 v electrolytic capacitor d1/d2/d3/d4 4 1n4007 do-41 d13 1 swtth1rl06 st do-41
bill of material AN4213 38/42 docid023984 rev 2 d6 1 1n4148 do-35 d8/d9 2 omitted d12 1 ll4148 smd 1406 d7 1 zener 16 v do-41 ptc 2 600 /120 c tdk/epc b59884c0120a070 ntc 1 2.5 tdk/epc b57236s0259m0 fuse 1 1.6 a/250 v serie tr5 l1 1 2x10mh/1a magnetica: common mode inductor code: 02106 class code:1045.0017 l2 1 500 h/0.81a magnetica: pfc inductor code: 06535 class code:2216.0001 l3/l4 2 1.5 mh/0.6a/2a pk magnetica: ballast inductor code: 07056 class code:1956.0007 q1/q2/q3 3 stl13n60m2 n-channel 600 v, 0.39 ? typ., 7 a mdmesh ii plus? low qg power mosfet in a powerflat? 5x6 hv package u3 1 l6562a st pfc driver so-8 u4 1 l6569 st hb driver so-8 table 4. board bill of material (continued) reference qty value/part number description
docid023984 rev 2 39/42 AN4213 layout layers appendix c layout layers figure 31. bottom layout layer figure 32. top layout layer figure 33. silkscreen top figure 34. silkscreen bottom am17345v1 am17346v1 am17347v1 am17348v1
reference AN4213 40/42 docid023984 rev 2 9 reference 1. an2761 application note
docid023984 rev 2 41/42 AN4213 revision history 10 revision history table 5. document revision history date revision changes 31-jul-2013 1 initial release. 12-may-2014 2 ? updated: section 6 ? updated: figure 27 , 28 , 29 and table 3 ? updated: table 4 ? minor text changes
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